1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multi-layer wiring structure, and, in particular, to a method of manufacturing a semiconductor device including a process of forming via holes having different depths by etching an insulating film such as an oxide film.
2. Description of the Related Art
FIG. 1 shows a sectional view of a semiconductor device of the related art in a condition in which via holes have been formed. An interlayer insulating film 8 is formed on a semiconductor substrate 2 including a device-isolating region 4 and a gate electrode 6. On the interlayer insulating film 8, wiring layers 16 (16a, 16b) are formed, as a result of AlCu films 10 (10a, 10b), Ti films 12 (12a, 12b) and TiN films 14 (14a, 14b) being deposited, at predetermined positions. On the interlayer insulating film 8 including the wiring layers 16a, 16b, an interlayer insulating film 18 is formed and is planarized through conventional planarization. In the interlayer insulating film 18, a shallow via hole 20a and a deep via hole 20b are formed above the wiring layers 16a and 16b, respectively.
When such via holes having different depths are formed through conventional dry etching, an underlying pattern located below a shallow via hole is damaged seriously in comparison to an underlying pattern located below a deep via hole. As a result of the damage, the contact resistance value of the via hole increases, variation of the contact resistance value of the via hole increases and, thus, reliability of a semiconductor device is degraded.
For example, in a case where inter-wiring-layer via holes are formed, through conventional dry etching, when underlying wiring layers 16a, 16b include AlCu films 10a, 10b, Ti films 12a, 12b and TiN films 14a, 14b, a via hole 20a in which both the TiN film 14a and the Ti film 12a of the underlying wiring layer 16a are etched through to the bottom thereof and a via hole 20b in which the TiN film 14b and the Ti film 12b of the underlying wiring layer 16b remain are formed above the same substrate 2 depending on thickness of a planarized interlayer film 18. In particular, in the via hole 20a in which the TiN film 14a and the Ti film 12a are etched through to the bottom thereof, Al of the AlCu film 10a of the underlying wiring layer 16a reacts to a gas of a CF family which is an etchant, and a low-volatile fluoride 22 is formed and is deposited on the sidewall of the via hole 20a. The fluoride 22 increases the contact resistance of the via hole 20a and increases variation of the resistance value. Further, during a degassing process on the order of 500xc2x0 C. performed before an upper wiring layer is formed, Al of the AlCu film 10a, exposed at the bottom of the via hole 20a as a result of the TiN film 14a and the Ti film 12a being etched through to the bottom thereof, may blow out, and, as a result, short-circuiting between wiring patterns may occur.
Thus, when via holes having different depths are formed in a conventional etching method, damage caused to underlying patterns located below the via holes is different depending on the depths of the via holes. In particular, reliability of a shallow via hole is greatly degraded.
In order to solve such a problem, methods which will be described below have been proposed.
In order to eliminate the difference between etching times required for forming respective via holes due to the level difference between respective metallic wiring layers caused by field oxide layers or the like, the following method has been proposed in Japanese Laid-Open Patent Application No. 7-122634: An interlayer insulating film including a film having a low etching rate, a film having a high etching rate and a film having a low etching rate when a predetermined etching gas is used, in the stated order, is formed, wherein each film having the low etching rate has a uniform thickness and the film having the high etching rate has a planer surface. In this method, an organic silicon compound including a CF radical is used as the film having the high etching rate. In the interlayer insulating film formed on the respective metallic wiring layers, although the thickness of each layer having the low etching rate is uniform, the thickness of the layer having the high etching rate varies. However, because the etching time required for forming the via holes in the film having the high etching rate is approximately equal regardless of the depth, it is possible to equalize the etching times required for forming the respective via holes.
Another method has been proposed in Japanese Laid-Open Patent Application No. 9-148270. In this method, for a variation in a film thickness of a film to be etched which variation is caused by an underlying structure (a level variation, etc.), an etching mask is formed such that aspect ratios (depths of via holes/diameters of the via holes) after etching of the via hole formed in a thin-film area and the via hole formed in a thick-film area are approximately equal to each other. As a result of the aspect ratios of the respective via holes being approximately equalized, etching completion times required for forming the via holes are approximately equalized, and, thereby, underlying patterns are prevented from being adversely affected.
Another method has been proposed in Japanese Laid-Open Patent Application No. 8-236619. In this method, an interlayer insulating film is a multi-layer film, and the respective films of the multi-layer film are deposited such that the etching rate increases sequentially starting from the substrate-side film, that is, the film having an etching rate which is extremely low in comparison to the other insulating films is formed nearest to the substrate. By using such an interlayer insulating film, the etching margin is ensured even at a thin part of the interlayer insulating film, and, thus, over-etching at the thin part thereof is prevented.
Another method has been proposed in Japanese Laid-Open Patent Application No. 9-17862. In this method, on a wiring pattern above which a via hole is formed and a planarized interlayer insulating film is thin, a film of a material having a low etching rate is previously formed. As a result of the film of the material having the low etching rate being formed at a specific position, an etching margin is ensured even at a thin part of the interlayer insulating film, and, thus, over-etching at the thin part thereof is prevented.
However, in the method disclosed in Japanese Laid-Open Patent Application No. 7-122634, the organic silicon compound including the CF radical is used as the film having the high etching rate. If this film is exposed on the sidewall of the via hole at a time of photoresist removal using O2 after etching, a chemical reaction occurs, and, thereby, the via hole may be damaged. In order to prevent this film from being exposed inside the via hole, it is necessary to perform an etch-back process such that the organic silicon compound is prevented from remaining at a position at which the via hole is formed. As a result, a number of processes to be performed increases, and variation in thickness of the interlayer insulating film increases.
In the method disclosed in Japanese Laid-Open Patent Application No. 9-148270, in order to equalize the etching times required for forming the via holes having the different depths, it is necessary to vary the diameters of the via holes depending on the depths thereof. Such a manner is not a practical one.
In the method disclosed in Japanese Laid-Open Patent Application No. 8-236619, etching is performed on the plurality of films having different etching rates at the same time. Therefore, control of the shapes of the via holes is difficult.
In the method disclosed in Japanese Laid-Open Patent Application No. 9-17862, the process of previously forming the film of the material having the low etching rate at the bottom of the interlayer insulating film is added. Further, after etching is performed on the interlayer insulating film, a process of removing the above-mentioned film of the material having the low etching rate is necessary to be performed. Thus, the number of processes increases and the processes are complicated.
An object of the present invention is to improve reliability of via holes and wirings as a result of controlling and equalizing damage caused to underlying patterns at the bottom of the via holes having different depths, when the via holes having the different depths are formed through dry etching.
A method of manufacturing a semiconductor device, according to the present invention, in which an interlayer insulating film is formed on an underlayer having a level variation, the surface of the interlayer insulating film being planarized, upper wiring layers and lower wiring layers being electrically connected through via holes formed in the interlayer insulating film so that a multi-layer wiring is provided, comprises the steps of:
a) forming a lowest-layer insulating film of the interlayer insulating film on the underlayer, the etching rate for the lowest-layer insulating film changing in response to change in flow rate of a predetermined etching reactive gas in a first manner;
b) forming at least one upper-layer insulating film of the interlayer insulating film on the lowest-layer insulating film, the etching rate for the at least one upper-layer insulating film changing in response to change in flow rate of the predetermined etching reactive gas in a second manner different from the first manner;
c) planarizing the surface of the at least one upper-layer insulating film;
d) forming a photoresist on the at least one upper-layer insulating film, the photoresist having openings at positions at which the via holes are formed in the lowest-layer insulating film and the at least one upper-layer insulating film;
e) etching the at least one upper-layer insulating film below the openings under a condition in which the flow rate of the predetermined etching reactive gas is such that the etching rate for the lowest-layer insulating film is low;
f) etching the lowest-layer insulating film below the openings under a condition in which the flow rate of the predetermined etching reactive gas is such that the etching rate for the lowest-layer insulating film is high;
g) removing the photoresist; and
h) forming the upper wiring layers above the via holes.
Thus, in the semiconductor-device manufacturing method according to the present invention, the lowest-layer insulating film and the at least one upper-layer insulating film are used. The etching rate for the lowest-layer insulating film changes in response to change in flow rate of the predetermined etching reactive gas. The etching rate for the at least one upper-layer insulating film under the condition in which the flow rate of the etching reactive gas is a first flow rate such that the etching rate for the lowest-layer insulating film is low is higher than the etching rate for the lowest-layer insulating film under the condition in which the flow rate of the etching reactive gas is the first flow rate. First etching (the step e)) is performed under the condition in which the flow rate of the etching reactive gas is the first flow rate. Then, second etching (the step f)) is performed under the condition in which the flow rate of the etching reactive gas is a second flow rate such that the etching rate for the lowest-layer insulating film is high.
The thicknesses of the at least one upper-layer insulating film at the positions at which the respective via holes are formed are different from each other because the underlayer has the level variation and the surface of the at least one upper-layer insulating film is planarized. In the step e) (first etching) in which the at least one upper-layer insulating film is etched at the positions at which the via holes are formed, the lowest-layer insulating film is also etched at the position at which the thickness of the at least one upper-layer insulating film is thin and the shallow via hole is formed, when the at least one upper-layer insulating film is etched through to the bottom thereof at the position at which the thickness of the at least one upper-layer insulating film is thick and the deep via hole is formed. However, in the step e), etching is performed under the condition under which the etching rate for the lowest-layer insulating film is low. Therefore, merely a slight depth of the lowest-layer insulating film is etched. After the at least one upper-layer insulating film is etched at the position at which the thickness of the at least one upper-layer insulating film is thick and the deep via hole is formed so that the lowest-layer insulating film is exposed at this position, the step f) (the second etching) is performed. In the step f), the lowest-layer insulating film is etched at the positions at which the respective via holes are formed. As a result, it is possible to control the etched amount in thickness of the underlying pattern (lower wiring layer) at the position at which the shallow via hole is formed to be sufficiently small under the condition in which a predetermined over-etching ratio is achieved for the deep via hole. Thereby, it is possible to equalize the conditions of the bottoms of the respective via holes and to form the via holes and wirings having high reliability.
When the etching rate for the lowest-layer insulating film is equal to or less than ⅕ of the etching rate for the at least one upper-layer insulating layer in the first etching (the step e)), it is possible to sufficiently control the depth of the lowest-layer insulating film etched in the first etching at the position at which the shallow via hole is formed. As a result, it is possible to effectively reduce the depth of the underlying pattern (lower wiring layer) etched in the second etching (the step f)) at the position at which the shallow via hole is formed.
When a silicon oxide film is used as the lowest-layer insulating film and a gas including C4F8 is used as the etching reactive gas, it is possible to sufficiently change the etching rate for the lowest-layer insulating film by adjusting the flow rate of the gas including C4F8.
Other objects and further features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.